The present invention relates to the fabrication of integrated circuits on semiconductor substrates, and more specifically, the present invention relates to a method for fabricating an integrated circuit having a combination of transistor gate electrodes formed using conventional processing techniques and a damascene processing technique in accordance with the present invention.
As greater and greater number of devices and circuits become possible on semiconductor integrated circuits, the desire to integrate more system function onto a single chip grows as well. Logic circuits process, while memory circuits store, information, and the two are used in tandem to add xe2x80x9cintelligencexe2x80x9d to electronic products. The two functions have been provided on separate chips, adding complexity and cost to the final product. There is an increasing need to join both memory and logic circuits together on the same chip.
In the recent years, advances in the semiconductor process technologies have dramatically decreased the device feature size and increased the circuit density and performance on integrated circuit chips. One of the more common integrated circuit devices is a field effect transistor (FET) which is used extensively for Ultra Large Scale Integration (ULSI). Typically, these FETs are formed using a predetermined number of polysilicon gate electrodes and self-aligned source/drain contact areas. Conventional FETs are generally fabricated by patterning polysilicon gate electrodes over a thin gate oxide layer formed on a single crystal semiconductor substrate. This gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned source/drain areas in the semiconductor substrate adjacent to the sides of the gate electrode. A channel is formed in the semiconductor substrate and includes a channel length which is defined as the distance from the source junction to the drain junction under the gate electrode.
With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on a single chip. For example, dynamic random access memory (DRAM), nonvolatile memory (NVM), and similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically formed of logic circuits for addressing the memory cells, with other peripheral circuits functioning as read/write buffers and sense amplifiers.
The FET of a semiconductor integrated circuit controls current conduction from a source region to a drain region by application of voltage to a gate conductor. If the gate conductor is insulated from the source-drain conduction channel, the device is called an insulated gate FET. The most common gate structure is that of metal oxide semiconductor (MOSFET).
Dopant atoms are introduced into MOSFETs for specific purposes such as to control threshold voltage, dope gate conductors, or to control substrate currents, with adverse side effects accepted as necessary by-products of dopant atom introduction.
The technology for dynamic random access memory (DRAM) circuits is optimized for density and low cost while the technology for high-speed logic functions may require dual work function gate conductor polysilicon transistor types which incorporate n-type or p-type dopants within the gate conductor of the transistor. This places additional problems of complexity and cost on the fabrication process.
Memory circuits achieve increased packing density with self-aligned diffusion contacts within the array. Gate structures used in conventional integrated circuit devices are typically of the same type throughout the integrated circuit device. For example, typical DRAM transistor gates are formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC). However, these conventional gate stacks preclude the formation of self-aligned silicide (salicide) layers which reduce resistance and improve device performance. Consequently, it would be advantageous and desirable to be able to employ two separate types of gate structures within the integrated circuit device to improve performance and be able to better tailor the electrical, chemical, and mechanical characteristics of the integrated circuit device.
The above-discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by the integrated circuit device of the present invention. The integrated circuit device comprises a semiconductor substrate having a combination of transistor gates formed using a conventional DRAM dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by selectively removing the dielectric-capped gate stack from selected regions of the semiconductor substrate and replacing the dielectric-capped gate stack with a second gate conductor which is preferably patterned using a damascene process. Accordingly, this second gate conductor is referred to as a damascene gate structure.
The integrated circuit of the present invention provides improved support device transistor performance by enabling the incorporation of dual work function doping along with self-aligned diffusion contacts, salicide gates, and dual gate oxide thickness devices. In addition, the process of forming the damascene gate structure of the present integrated circuit device provides an accessible self-aligned channel region generally below the damascene gate conductor. This accessibility to the self-aligned channel region permits greater flexibility in the formation of the damascene gate structure and the self-aligned channel region may be modified, e.g., by an ion implementation process, independently of source/drain ion implementation.
In another aspect, because a damascene process is preferably used to form the second gate conductor, a thin gate dielectric layer, e.g., oxide layer, which comprises a portion of the second gate conductor is selected independent from the first thin gate dielectric layer which forms a portion of the conventional first dielectric-capped gate stack. Independent control of the second thin gate dielectric layer, including the thickness thereof, results in improved performance and reliability in the integrated circuit device of the present invention.
The above-discussed and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description and drawings.